1. Field of the Invention
The embodiments discussed herein relate to a control device for a power conversion apparatus, the control device including a timing detection circuit which is needed to mutually correct an imbalance in current in a case where a plurality of power semiconductor elements is connected in parallel to constitute the power conversion apparatus, and to the power conversion apparatus including the power semiconductor elements therein.
2. Background of the Related Art
In power conversion apparatuses, power conversion is performed by switching and driving a power semiconductor element. In the power semiconductor element, the maximum current which one power semiconductor element is capable of feeding is limited in terms of physical properties and technically, and therefore when a load current exceeding this limit is needed, a plurality of power semiconductor elements is connected in parallel to increase the current capacity.
FIG. 9 illustrates a switching circuit formed by connecting two power semiconductor elements in parallel, FIG. 10 illustrates changes in current when two power semiconductors are switched, FIG. 11 illustrates an example of a timing detection circuit, and FIG. 12 is an explanatory view of the operation of the timing detection circuit.
In FIG. 9, an IGBT (Insulated Gate Bipolar Transistor) is illustrated as the power semiconductor element. This switching circuit is constituted by connecting the collectors of an IGBT 101 and an IGBT 102 and connecting the emitters thereof, and may constitute a high-side arm portion and a low-side arm portion in, for example, a totem pole output circuit of a power conversion apparatus.
The IGBTs 101 and 102 connected in parallel in this manner are turned on or turned off by simultaneous application of a pulse-like gate voltage to the gates thereof, respectively. At this time, when the current flowing into the collectors is designated as Ic, a current Ic1 flows into the IGBT 101 and a current Ic2 flows into the IGBT 102. Ideally, the current Ic is evenly distributed between the IGBTs 101 and 102 so as to satisfy Ic1=Ic2=Ic/2. However, in the transitional period of this switching operation, an imbalance may occur between the currents flowing into the IGBTs 101 and 102, respectively.
Such current imbalance is due to an individual difference in the element characteristics of the IGBT 101, 102, and/or due to a difference in the electrical characteristics in a gate wiring circuit.
Due to the above-described factors, if a difference (time difference) between the IGBTs 101 and 102 in the turn-on time and/or in the turn-off time occurs, a transitional current imbalance will occur between the IGBTs 101 and 102. For example, as illustrated in FIG. 10, assume that current first started to flow through the IGBT 101 and a little later current started to flow through the IGBT 102. In this case, at the turn-on time, the current flows only through the IGBT 101 and therefore in the period of a time delay difference Δtd, the current will concentrate on the IGBT 101 and a high current will flow therethrough. If the current concentration occurs, then the current exceeding the maximum rating flows, though for a short time, so that the IGBT 101 might be destroyed or the element temperature might abruptly rise to significantly degrade the element characteristics.
Therefore, it is proposed to reduce the current imbalance among a plurality of the IGBTs connected in parallel (e.g., see Japanese Laid-open Patent Publication No. 2014-230307). In this Japanese Laid-open Patent Publication No. 2014-230307, the turn-on and turn-off times of each IGBT are detected, and the turn-on and turn-off times of an IGBT which is turned on earlier are controlled so that the time delay difference Δtd becomes zero, i.e., so that the latter times are delayed. In this control, a variable gate resistor circuit is provided in a circuit which drives the gate of the IGBT and the resistance value of the variable gate resistor circuit is varied in accordance with the time delay difference Δtd. Thus, a plurality of IGBTs which is connected in parallel and is simultaneously driven is capable of reducing the current imbalance among the IGBTs.
The turn-on and turn-off times of the IGBT may be detected by a timing detection circuit illustrated in FIG. 11. The timing detection circuit of FIG. 11 detects the turn-on and turn-off times of the IGBT 101, for example, but also in the other IGBT 102, the turn-on and turn-off times are detected by a timing detection circuit having the same configuration.
This timing detection circuit includes a sense resistor Rs, a comparator 103, and a reference voltage source Vref. The IGBT 101 has a current sensing terminal that is formed by partially separating and partitioning the emitter region of the chip of the IGBT 101. A current corresponding to the area ratio between the current sensing terminal and the main emitter terminal will flow into this current sensing terminal as a sense current Is. This sense current Is flows to the ground through the sense resistor Rs connected to the current sensing terminal of the IGBT 101, so that a sense voltage Vs proportional to the emitter current is generated between the both ends of the sense resistor Rs. This sense voltage Vs is compared with a reference voltage source Vref in the comparator 103 and a signal Ipulse is output.
In the case where a reference voltage Vref is connected to the inverting input of the comparator 103 and the sense voltage Vs is connected to the noninverting input as illustrated in FIG. 11, this signal Ipulse rises when the sense voltage Vs exceeds the reference voltage source Vref and falls when the sense voltage Vs falls below the reference voltage source Vref as illustrated in FIG. 12. The rising of this signal Ipulse becomes the turn-on time of the IGBT 101, and the falling of the signal Ipulse becomes the turn-off time of the IGBT 101. Moreover, in the case where the reference voltage Vref is connected to the noninverting input of the comparator 103 and the sense voltage Vs is connected to the inverting input, this signal Ipulse falls when the sense voltage Vs exceeds the reference voltage source Vref and rises when the sense voltage Vs falls below the reference voltage source Vref. The falling of this signal Ipulse becomes the turn-on time of the IGBT 101, and the rising of the signal Ipulse becomes the turn-off time of the IGBT 101. The turn-on time is sent to a non-illustrated control circuit, where it is compared with the turn-on time of the IGBT 102, and the resistance value of the variable gate resistor circuit is controlled so that these turn-on times match.
Accordingly, the turn-on and turn-off times of the IGBTs 101 and 102 connected in parallel will be aligned to reduce the current imbalance between the IGBTs 101 and 102.
The above-described timing detection circuit detects the turn-on time and turn-off time of the IGBT by comparing the sense voltage Vs with the reference voltage source Vref. Here, in the case where the power semiconductor element is an IGBT, there is a problem that the turn-off of the IGBT is detected at a different time due to the current value of the collector current which had been flowing before the IGBT is turned off.
FIG. 13 illustrates a tail current that flows after an IGBT is turned off.
In an IGBT, due to turn-off, a collector current Ic sharply decreases and a tail current continues to flow immediately before the collector current becomes zero. That is, the shutoff of the collector current is performed by shorting or reverse-biasing between the gate and emitter of the IGBT, but at this time, the gate electric charge is discharged, the channel disappears, the supply of the base current is stopped, and then the IGBT starts to transition to a turn-off state. In this case, because there are a large amount of excess electrons and holes in an n− region as the accumulated charges, the collector current will not be immediately shut off but a tail current will flow. This tail current decreases gradually with a time constant that depends on the life time of the charges. Therefore, the larger the collector current Ic during turn-on, the longer the tail current continues to flow.
Accordingly, the turn-off time detected by the comparator 103 will significantly vary with the magnitude of the collector current Ic during turn-on. Here, in FIG. 13, a case will be described where the reference voltage source Vref is set equal to a voltage that corresponds to the sense voltage Vs when the collector current Ic of 5 A flows. When the collector current Ic is 10 A, the turn-off time by the timing detection circuit is 1.23 microseconds (μsec) after the measurement started, while when the collector current Ic is 150 A, the turn-off time by the timing detection circuit is 1.45 microseconds (μsec) after the measurement started. Therefore, upon receipt of a signal indicative of the turn-off time from the timing detection circuit, a non-illustrated control circuit performs control to reduce a current imbalance, based on a signal which varies with the magnitude of the collector current Ic. As described above, once an error occurs in which the turn-off time varies with the magnitude of the collector current Ic during turn-on, then even if the time delay difference Δtd is controlled so as to become zero, it will not actually become zero. As the result, the accuracy of the control to reduce the current imbalance will significantly decrease.